Integrated circuit junction isolation structure

ABSTRACT

A PLANAT MONOLITHIC SEMICONDUCTOR INTEGRATED CIRCUIT MASTERSLICE STRUCTURE COMPRISING A SURFACE FROM WHICH A PLURALITY OF REGIONS OF DIFFERENT CONDUCTIVITY TYPES EXTEND INTO TH CHIP TO PROVIDE THE ACTIVE AND PASSIVE DEVICES OF THE CIRCUIT AND HAVING A SUBSTANTIALLY CONTINUOUS ISOLATION RETION OF ONE OF SAID CONDUCTIVITY TYPES ALSO EXTENDING FROM SAID SURFACE TO FORM ISOLATION JUNCTIONS WITH REGIONS OF OPPOSITE CONDUCTIVITY TYPES ABUTTING THE ISOLATION REGIONS. SUBSTANTIALLY ALL ISOLATION REGIONS SURROUNDINT ACTIVE AND PASSIVE DEVICES IN THE CIRCUIT HAVE A UNIFORM PLANAR WIDTH. THE UNIFORM WIDTH OF THE ISOLATION REGIONS APPEARS TO REDUCE STACKING FAULTS AND SIMILAR CRYSTALLOGRAPHIC DEFECTS IN EPITAXIAL LAYERS IN WHICH THE INTEGRATED CIRCUITS ARE FORMED. SUCH FAULTS CONTRIBUTE TO &#34;PIPES.&#34;

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 0.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Ofiice makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED JANUARY 1, 197i T918,007 INTEGRATED CIRCUIT JUNCTION ISOLATION STRUCTURE Mario A. Batfista, Ridgefield, Conn., and Larry E. Freed, Poughkeepsie, and Richard S. Hal-bison, William J. Nestork, and James R. Struk, Wappingers Falls, and Daniel Tuman, Beacon, N.Y., assignors to International Business Machines, Inc., Armonk, N .Y.

Continuation of application Ser. No. 239,173, Mar. 29, 1972. This application June 6, 1973, Ser. No. 367,603 Int. Cl. H011 5/00 US. Cl. 317235 2 Sheets Drawing. 11 Pages Specification" A planar monolithic semiconductor integrated circuit mastcrslice structure comprising a surface from which a plurality of regions of different conductivity types extend into the chip to provide the active and passive devices of the circuit and having a substantially continuous isolation region of one of said conductivity types also extending from said surface to form isolation junctions with regions of opposite conductivity types abutting the isolation regions. Substantially all isolation regions surrounding active and passive devices in the circuit have a uniform planar width.

The uniform width of the isolation regions appears to reduce stacking faults and similar crystallographic defects in epitaxial layers in which the integrated circuits are formed. Such faults contribute to pipes.

Jan. 1, 1974 M, AJBATTISTA ETAL lNTEGRATED CIRCUIT JUNCTION ISOLATTON STRUCTURE 2 Sheets-Sheet 1 Filed March 29, 1972 PRIOR ART k Jan. 1, 1974 M BATTlSTA HAL T918,007

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